Yufei Shi
Master's student studying Electrical and Computer Engineering at Carnegie Mellon University.
Contact: yfshi@ cmu.edu or contact@ shiyufei.com
PGP Public Key Fingerprint: 175C2EAA2C99EB415B0341F382FFF49FF55B077D
Hello!
I am a Master's (and ex-undergraduate) student in Electrical and
Computer Engineering at Carnegie Mellon University, having graduated
with a B.S. in ECE with University Honors in May 2024 also at CMU.
I am advised by
Prof. Brandon Lucia, and a
member of the
abstract research group.
You can find my
CV here
and my
resume here.
Research
I am interested in doing research on the boundary of computer
architecture and computer systems, with a particular emphasis on
optimizing computing performance and efficiency beyond traditional
scaling.
I am currently working on projects centered around the themes of
spatial dataflow architectures, parallelism, and concurrency.
Research on memory consistency of spatial dataflow architectures.
Problem Some pipelined spatial dataflow architectures lack a well-defined memory consistency model and often do not provide explicit guarantees about memory operations. Instead, they rely on the programmer's understanding of the microarchitecture to ensure correct program execution. This can lead to unpredictable memory behaviors, especially when data races occur.Goal Define memory ordering behaviors for Pipestitch-a recent pipelined spatial dataflow architecture—and provide programmers with memory ordering primitives to ensure consistent and predictable memory operations.
Approach Develop a memory consistency model for Pipestitch and implement microarchitectural support for memory ordering primitives (e.g. memory barriers), enabling explicit control over memory ordering. And apply this methodology to other similar architectures to enhance their memory consistency models and offer consistent programming mechanisms across various platforms.
Research on asynchronous programming for spatial dataflow architectures.
Problem Many spatial dataflow architectures struggle to efficiently implement irregular computations due to an abstraction inversion: they fail to leverage the architecture's inherent dataflow semantics to capture coarse-grain asynchronous parallelism. This leads to bloated programs with low utilization and poor performance.Goal Develop a language and architecture that preserve low-level dataflow semantics and enable efficient asynchronous parallel programming for spatial dataflow architectures.
Approach Implement asynchronous iterators and a set of task-parallel primitives to encode explicit asynchrony and queueing behavior native to dataflow. Support deadlock-free asynchronous task communication using hardware token queues and shared-memory synchronization with ISA extensions.
Teaching
- Fall 2024: Teaching Assistant for 18-344 Computer Systems and the Hardware-Software Interface
- Fall 2023: Teaching Assistant for 18-344 Computer Systems and the Hardware-Software Interface
- Summer 2023: Teaching Assistant for 18-213/18-613 Introduction to Computer Systems
- Fall 2022: Teaching Assistant for 18-213/18-613 Introduction to Computer Systems
- Summer 2022: Teaching Assistant for 18-213/18-613 Introduction to Computer Systems
- Spring 2022: Teaching Assistant for 18-213/18-613 Introduction to Computer Systems