Yufei Shi

I am a Master's (and ex-undergraduate) student in Electrical and Computer Engineering at Carnegie Mellon University, having graduated with a B.S. in ECE with University Honors in May 2024 also at CMU.

I am advised by Prof. Brandon Lucia, and a member of the abstract research group.

I am interested in doing research on the boundary of computer architecture and computer systems, with a particular emphasis on optimizing computing performance and efficiency beyond traditional scaling.

I am currently working on projects centered around the themes of spatial dataflow architectures, parallelism, and concurrency.

Research on memory consistency of spatial dataflow architectures.

Problem   Some pipelined spatial dataflow architectures lack a well-defined memory consistency model and often do not provide explicit guarantees about memory operations. Instead, they rely on the programmer's understanding of the microarchitecture to ensure correct program execution. This can lead to unpredictable memory behaviors, especially when data races occur.
Goal   Define memory ordering behaviors for Pipestitch-a recent pipelined spatial dataflow architecture—and provide programmers with memory ordering primitives to ensure consistent and predictable memory operations.
Approach   Develop a memory consistency model for Pipestitch and implement microarchitectural support for memory ordering primitives (e.g. memory barriers), enabling explicit control over memory ordering. And apply this methodology to other similar architectures to enhance their memory consistency models and offer consistent programming mechanisms across various platforms.